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How to co-simulate Verilog with Spectre ?? (Read 2958 times)
Faisal
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How to co-simulate Verilog with Spectre ??
Jul 04th, 2006, 9:04am
 
Hi,

I need to know if there exist a mechanism through which i can co-simulate my digitial design in a Verilog simulator lilke ModelSim/NC-Verilog and my analog design in Spectre ??

Faisal
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ACWWong
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Re: How to co-simulate Verilog with Spectre ??
Reply #1 - Jul 5th, 2006, 5:57am
 
Yes, you can use spectreVerilog (although this is an old tool) or AMSdesigner, both are standard tools from Cadence.

spectreVerilog uses spectre for analog and a sperate verilog executable for the digital. It is ok for large analog/small digital, but as you only simulate analog or digital at any one time, (it has two kernels, one analog, the other digital and the tool handles the interface between them) it might not be suitable for designs which have alot of analog to digital communication.

AMS designer is a replacement to spectreVerilog and is more efficient in handling both domains in one kernel. In experience its a bit of pig to setup correctly.

anyway you can find more infomation from cadence.

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jbdavid
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Re: How to co-simulate Verilog with Spectre ??
Reply #2 - Aug 11th, 2006, 1:10am
 
There is LOTS more info on this in the AMS simulators section of this forum

and at http://www.bmas-conf.org

ncsim -ams uses the spectre solver for the transitor part of the simulation (and any Verilog-A and analog part of Verilog-AMS models.. )
Rest is event driven.
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jbdavid
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Faisal
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Re: How to co-simulate Verilog with Spectre ??
Reply #3 - Aug 11th, 2006, 2:44am
 
Yes, I am now using AMS Simulator and its indeed very helpful in exploring designs at the architectural/behavioral level
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