TSMC models have lots of problems.
If you are doing anything outside of digital logic you need to patch the models quite a bit.

Here see my list of common problems:

http://www.effectiveelectrons.com/foundrymodels.html

take a look at the list on the bottom of the page.

As  well, how to look the problem over and understand it:

http://www.chipdesignmag.com/display.php?articleId=438&issueId=16

And my other commentary on this topic:

http://www.elecdesign.com/Articles/ArticleID/8937/8937.html

As you can see, it is a pet peeve of mine, but with good reason.

Hope that helps -
Jerry

SMIC ?? Hm, I have not designed on their processes before so I have not been into their model sets.

Take a look at my chip design article -
http://www.chipdesignmag.com/display.php?articleId=438&issueId=16
thats my "poke around and look inside" method of determining if models are any good.

The quick questions:
- are all passive models three wire with parasitics?
- do all passives have thermal variance in them?
- are the MOS models BSIM 3v2 or later?
- is flicker noise present in the CMOS models?

If the answer is yes to all of the above, then you can usually say that some care was taken in developing the models.

Also remember the models can be BSIM2500.99  :D
but that does not mean that the numbers put into the model are correct.

I did a foundry model audit for 65nm recently, the models were BSIM4.5, but a large portion of the parameters were either zero, or not set and went to default values.  Essentially it was a Level 13 (the old BSIM 1) model due to the fact that none of the numbers were set properly.

The most common problem with the transistor models are:
noise not properly set,
capacitance distributed improperly,
derivative terms (transconductance et. al.) not fitting properly.

If you can post a transistor model, a resistor model and a cap model I can take a quick look.

Jerry