I'm a novice at Verilog-A, but I've got the book and I'm learning.  I'm using Spectre to simulate a DAC at the transistor level, and am using a Verilog-A block to generate "digital" stimulus for the transistors.  I'm using a transition statement to create a finite rise and fall time for my signals, but I continually get the error:

Convergence difficulties resulted in error requirements being unsatisfied.

The convergence errors come at the instant the transistion starts, as if the "corner" is too sharp, and the simulator can't handle it.  I was able to get around the problem for a while by slowing the transition from 100 ps to 300 ps, then inserting a simple RC filter at the interface. so it seems that it smooths the signal at the transistor inputs enough that they don't get lost.   But now I'm trying to run a Monte Carlo sim, and the error is back, and to the point where I can't complete a simulation.  I tried inserting a $discontinuity(1); after my @cross, and that helps, but I still get warnings, and each Monte Carlo run that actually manages to finish still takes 10 times as long to run as the reference Spectre one.

So, is there something inherently different about the Monte Carlo simulation that is causing problems?  Is there something special I should be doing at the output of a decoder to make it so I don't need the RC filters?  For now I plan to keep reading and hopefully I'll find that there is something I should be doing that I just haven't learned yet, but from what I understand, the transition statement should be enough.  

I'm open to suggestions...

Here is the code for a thermometer decoder that takes a 7 bit binary or twos complement input and converts it to a 128 bit thermometer coded output.  Yes, I know that there are 256 output bits,  this is a work in progress so just ignore that part...



module therm8_256(out, ana_out, in);

output [255:0] out;
electrical [255:0]out;
input [6:0] in;
electrical [6:0] in;
output ana_out;
electrical ana_out;

parameter real vtrans = 1.65 from (-15:15);         // Digital clock switching voltage.
parameter real vout_low = 0.0 from [-15:15);       // Digital output low voltage
parameter real vout_high = 3.3 from (vout_low:15]; // Digital output high voltage
parameter real trise = 250p from (0:1m];           // Rise/fall time of digital outputs
parameter integer twosComp = 0 from [0:1];           // 1 if input is in twos complement
                                           // 0 if offset binary

integer in_value, i, out_value_sum;
real out_value[255:0];


analog begin
     generate i (6, 0) begin
     @(cross(V(in[i])-vtrans,0))
     $discontinuity(1);
     end // generate
     
     in_value = 0;
     
     if (twosComp == 0) begin            // read msb of input bits, offset binary
           if ( V(in[6]) > vtrans )
                 in_value =  in_value + pow(2,6);
           end // if twosComp
           
     if (twosComp == 1 ) begin            // read msb of input bits, 2s complement
           if ( V(in[6]) < vtrans )
                 in_value =  in_value + pow(2,6);
           end // if twosComp            
     
     generate i (0, 5, 1) begin            // read remaining input bits
     
           if ( V(in[i]) > vtrans )      begin
                 in_value = in_value + pow(2,i);
           end //if
     
     end // generate
     
     out_value_sum = 0;
     
     for (i=0; i < 256; i = i +1) begin      // write output value
           if( i < in_value) begin
                 out_value[i] = vout_high;
                 out_value_sum = out_value_sum +1;
                 end else out_value[i] = vout_low;            
     end // for
                 
     generate i (0, 255, 1) begin      // perform output transitions
           V(out[i]) <+ transition(out_value[i],0,trise);
     end // generate
     
     V(ana_out) <+ transition(out_value_sum,0,trise);
     // end  // @      
end //analog


endmodule

I have been able to clear up all the errors by adding a clock line and only using the clock signal in my @cross statement.  I suppose that simultaneously switching inputs may have caused some confusion in the code execution.  I was hoping I wouldn't have to use a clock because I wanted to be able to simulate the effects of glitches due to timing mismatches in the input signals, but I suppose there are other ways to acheive that.  Thanks for your help.