can you write the needed PW into a file? then read the file from the verilogams ..?

jbd

This I don't know..
I was thinking that due to differences in time scale you are probably not looking for a realtime solution..
so if you can capture the PW from the external source into a file,
the your verilog model can read those in and generate the voltage in the simulation..

of course you may not need that exact solution..
capture the data in VCD format (see Verilog-XL reference or IEEE - 1364 )
and use a tool like ncgentb to turn the data into 1-0's in a verilog testbench for your circuit
capture the data in PWL format (see the spectre reference manual) and
read it into a spectre simulation with a VPWLF (or vsource - set to PWL type, read data from a file)

If you DON'T need to cature the data from an external source, (you said in your original question that this was
a requirement - then complain that you might need to genereate the PW outside your model.. which I find a little confusing)
you might want to write a verilog-A or verilog model to generate a "random" PW signal..
one type would be a PRBS of a certain bit length at a fixed period..
OR you could use a voltage input to represent duty cycle (0-1v) and run that through a V-> duty cycle circuit.

If you were coming to me as a customer there is a LOT more I need to know to make any kind of recommendation on an approach.
I hope the suggestions above help.