Sometime ago when I uploaded a new paper to the site, I forgot to mention it. This post is to correct this lapse.

Paul Muller and Yusuf Leblebici (http://www.designers-guide.org/Modeling/JTOL_rev1.0.pdf) discuss the behavioral modeling of a pattern generator including various types of data jitter for jitter tolerance analysis of high-speed serial link receivers during the design phase. The presented model can be used both during the system-level design exploration and the following transistor-level design phases. First, jitter tolerance of clock recovery circuits is explained and the different natures of jitter applied to the data test pattern are introduced. Then, a behavioral model of the serial data pattern generator is presented, which includes these jitter components and delivers the jitter-affected data used to stimulate the receiver’s clock recovery circuit. Finally, the detailed VHDL-AMS model is introduced and its parameter definitions are discussed.