Hello.

I've been reading the forum for some time and found it invaluable in helping any problems I've encountered during my short Verilog modelling career. However, there seems to be no ready made answer in the forum to the particular problem I'm facing now so I'm finally a registered user. This seems to be my last chance of enlightenment to the solution so fingers crossed!

I've been asked to create a digital behavioural model for an IO cell using Verilog.

My port declarations are shown below:-

Code:

module SIO2D25CSH (IN, EN, VDDP, VSSP, VDDC, VSSC, IO, ZI);

input IN;		// Input voltage terminal.
input EN;		// Enable pin.
inout VDDP;		// Supply voltage.
inout VSSP;		// Ground.
inout VDDC;		// Dummy pin.
inout VSSC;		// Dummy pin.
inout IO;		// In/output voltage terminal.
output ZI;		// Secondary output voltage terminal.

reg ZI;
reg out_io;

real out_temp;		// Temporary register for output signal. 

The specifications of the model are as follows:-

• When EN is HIGH ---> IO will be used as an output ∴ IO = IN and ZI = IN.

• When EN is LOW ---> IO will be used as an input ∴ ZI = IO.

After trying several different methods with varying success, my model at the moment after going back to basics (which gives a simulation as close to what I desire yet) is as follows:-

Code:

  always @(IN or EN or IO) begin

    assign out_io = IO;

    assign out_temp = EN ? IN : IO;

    out_io <= out_temp;
    ZI <= out_temp;

  end

endmodule 

This gives me the following simulation results:-



As you can see, ZI works as required. However, IO only ever follows net19 (the signal fed to IO when in use as an input). I suppose what I am essentially asking is if it is possible to make an inout switch between being an input and output. Or more likely, are my assignment statements for IO are incorrect?

Any help or advice would be very much appreciated. I thank you in advance.

Stuart