Dear,

  I wrote the following in the analog block in the verilog-a module.
 
analog begin

     @ ( initial_step ) begin
      sigout_file = $fopen( "out.m" );
      $fstrobe(sigout_file,"%% %s sampled at %g Hz.", "Sine Wave", 1/tsample);
      $fstrobe(sigout_file,"%% Generated by Spectre from instance `%M'");
                $fstrobe(sigout_file,"outv=[ ");
      next_sample_time = tsample;
     end
   

     @ ( timer( next_sample_time )) begin
      if (log_time == 1 ) begin
                    $fwrite(sigout_file, "%-.10g\t%-.10g", $abstime, V(sigin));
      end else begin
                    $fwrite(sigout_file, "%-.10g ", V(sigin));
                end
     //end
               if ($abstime >= next_sample_time)
                     next_sample_time = next_sample_time + tsample;
     end

     @ ( final_step ) begin
               $fstrobe(sigout_file, "]");
               $fclose(sigout_file);
     end
end

But the fstrobe commands in the initial block are executed twice.
(In the output file, there are 2 duplicates of sentences at the head.)
I don't get what's wrong with this initial keyword.

Thank You

how we probe those local variables inside verilog-a model in spice simulation?

This will make debug possible.