Here's something I wrote a while ago for testing an eye diagram calculator function. Not quite what you want, but it might give you a few clues:
Code:// VerilogA for test, randedges, veriloga
`include "constants.h"
`include "discipline.h"
module randedges (op);
output op;
electrical op;
parameter real period = 50.0n from (0:inf);
parameter real sd = 1.0n;
parameter real vh=5.0;
parameter real vl=0.0;
parameter real tdel=10.0n from [0:period);
parameter real trise=2.0n from [0:period);
parameter real tfall=2.0n from [0:period);
parameter integer seed = 23133;
integer cycle,bit,vseed;
real next,vout_val,randnum;
analog begin
@(initial_step("ac","tran","dc","xf" )) begin
vseed=seed;
cycle=1;
next = cycle*period/2.0;
bit=0;
vout_val=vl;
end
$bound_step(period/4.0);
@ (timer(next)) begin
bit=~bit;
cycle=cycle+1;
vout_val=(bit==0 ? vl : vh);
//randnum=($rdist_normal(vseed,0,1))*sd;
randnum=$rdist_normal(vseed,0,1);
randnum=randnum*sd;
//$display ("Random number is %g sd is %g", randnum,sd ) ;
next = cycle*period/2.0+randnum;
//$display("Current: %g next: %g rand %g cycle %d",$abstime,next,randnum,cycle);
end
V(op) <+ transition(vout_val,tdel,trise,tfall);
end
endmodule
Regards,
Andrew.