Hello,

I am trying to generate a signal with constant period, T, but random duty-cycle. Essentially, I would like to obtain a clk-like signal whose "on-time" is random and uniformly distributed between 0 and let's say 0.1T.

I can generate random bit streams with:
@(timer(start, period))
x = ($random(y) >= 0) ? 1 : 0;

but here the period of the signal x will vary and also I cannot set limits on the duty cycle maximum and minimum.

Can anyone suggest a way?
Thanks for any tips.

Here's something I wrote a while ago for testing an eye diagram calculator function. Not quite what you want, but it might give you a few clues:

Code:

// VerilogA for test, randedges, veriloga

`include "constants.h"
`include "discipline.h"

module randedges (op);
output op;
electrical op;
parameter real period = 50.0n from (0:inf);
parameter real sd = 1.0n;
parameter real vh=5.0;
parameter real vl=0.0;
parameter real tdel=10.0n from [0:period);
parameter real trise=2.0n from [0:period);
parameter real tfall=2.0n from [0:period);
parameter integer seed = 23133;

integer cycle,bit,vseed;
real next,vout_val,randnum;

  analog begin

   @(initial_step("ac","tran","dc","xf" )) begin
	vseed=seed;
	cycle=1;
	next = cycle*period/2.0;
	bit=0;
	vout_val=vl;
    end

    $bound_step(period/4.0);

    @ (timer(next)) begin
	bit=~bit;
	cycle=cycle+1;
	vout_val=(bit==0 ? vl : vh);
	//randnum=($rdist_normal(vseed,0,1))*sd;
	randnum=$rdist_normal(vseed,0,1);
	randnum=randnum*sd;
	//$display ("Random number is %g sd is %g", randnum,sd ) ;
	next = cycle*period/2.0+randnum;
	//$display("Current: %g next: %g rand %g cycle %d",$abstime,next,randnum,cycle);
    end

    V(op) <+ transition(vout_val,tdel,trise,tfall);

  end

endmodule
 

Regards,

Andrew.