Hi all,
I'm new to writing verilog-A modules.  I need some help (or a pointer to what book to buy to help!).  
I am setting up a verilog-A library to handle logic.  I have made an inverter module that models gate capatitance nicely.  I want to do the same for the multiple input gates, and retain the usefulness of the module for any number of inputs.  I have the module working with an appropriate cap on the first input of a 2 input nand, but can't figure out how to make the the cap 'increment' (for lack of a better word) to appear on all inputs.   Any pointers to material on this subject, or any help at all would be appreciated.   My code is below: first the model statment, then the module.  Please note that I found a bug in the spice engine that we use, and there is a hack in the code to workaround this until the software vendor fixes it.  The module is otherwise from eda-stds.org/verilog-ams/ more or less in tact, except for the Cap that I added.
Thanks for taking the time to read all of this!
John

*model statment
* nand2a
.model NAND2A_VLG VLG MODULE = nandg
+ vth = 1.4
+ tdelay = 2p
+ trise = 1p
+ tfall = 1p
+C_IN = 17e-15
+size = 2
*

// Now the module
////////////////////////////////////////////////////////////////////////
// NAND gate
//
module nandg (in,out);

parameter real size      = 2 from [2:inf),
               vout_high = 3.3,
               vout_low  = 0 from (-inf:vout_high),
               vth       = 1.4,
               tdelay    = 5n from [0:inf),
               trise     = 10n from [0:inf),
               tfall     = 12n from [0:inf);
              input [0:size-1] in;
output           out;
voltage          in, out;

integer in_state[0:size-1];
integer out_state;
integer i;
real    vout;

// electrical gnd;
// ground gnd;
parameter real       C_IN     = 0 from [0:inf);
capacitor #(.c(C_IN))  cin(in[i]);
 
analog
begin
  @(initial_step)
    for(i=0; i<size; i=i+1) in_state[i] = 0;

  generate i (0, size-1)
  begin
    @(cross(V(in[i]) - vth))
    begin
      // Hack to workaround spice problem
      for(i=0; i<size; i=i+1) in_state[i] = V(in[i]) > vth;  
      // Hack to workaround spice problem End
      out_state   = 1;
      for (i=0; i<size; i=i+1) begin
        if (!(out_state && in_state[i])) out_state = 0;
      end
      if (out_state) vout = vout_low;          // Inversion
      else           vout = vout_high;
    end
  end

  V(out) <+ transition(vout,tdelay,trise,tfall);
end
endmodule
//
////////////////////////////////////////////////////////////////////////

It is odd that the same variable i is used as the index for both the for loops, and for the generate loop that contains them.

To add capacitors to every input, you should do it behaviorally by adding
Code:

    I(in[i]) <+ C_IN*ddt(V(in[i])); 

inside the generate statement. And if you do this, you will need to convert the ports from voltage to electrical as Geoffrey suggests.

-Ken

parens are not balanced.

Also, you will need to do something about using i as the index variable for both the for loops and the generate.

-Ken

altaj wrote on Feb 28^th, 2007, 3:30pm:


I'm not sure you got Ken's point.  You've got
 generate i (0, size-1)

so you should change your for loops to
for (j=0; j<size; j=j+1)

Also: you have
 generate
 I<+
 begin
whereas I'd expect you should have had
 generate
 begin
   I<+

that is, the capacitor contrib I<+ should be *inside* the begin/end for the generate.

altaj wrote on Mar 1^st, 2007, 2:59pm:


You've still got a problem.

Quote:

Indeed!

altaj wrote on Mar 2^nd, 2007, 1:14pm:


That's simulator dependent, I think.  Some simulators treat a V-AMS module as a subckt, some as a built-in primitive (you don't see internal nodes of the diode when it has series resistance).

You could try doing the resistor with a contrib rather than an instantiated resistor:
I(sw,out) <+ V(sw,out) / RDSON;

You don't need both j and k, but it doesn't hurt.