altaj
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Posts: 11
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Geoffrey, I untangled the loop problems you pointed out, and this code seems to work okay, anyway it behaves like a nand gate. I hope I did not go to far adding new variables (j & k). Note that due to the software vendors bug, I have to use the explicit caps for now. (They say their software does not "handle verctors correctly".)
ALso, a question: I have put a resistor in to model the output resistance. It is working fine, but I don't know how to properly define the variable for sw. Right now it shows up in simulation results the same as "in" and "out" do, and I would rather it did not. I tried defining it as "real sw;" but I get an error, so I left it as electrical. Is everything defined as "electrical" automatically passed to spice as a voltage or current? I assumed it would be limited to what was in the in and out declarations, but that does not seem to be the case.
code: //////////////////////////////////////////////////////////////////////// // NAND gate // module nandg (in,out); parameter integer size = 2 from [2:inf); parameter real C_IN = 0 from [0:inf), RDSON = 0 from [0:inf), vout_high = 3.3, vout_low = 0 from (-inf:vout_high), vth = 1.4, tdelay = 0.1p from [0:inf), trise = 0.1p from [0:inf), tfall = 0.1p from [0:inf); input [0:size-1] in; output out; electrical in, out, sw;
integer in_state[0:size-1]; integer out_state; integer i,j,k; real vout; // implicit caps capacitor #(.c(C_IN)) cin0(in[0]); capacitor #(.c(C_IN)) cin1(in[1]); resistor #(.r(RDSON)) r1 (sw, out); //V(p,n) <+ r*I(p, n); //
analog begin @(initial_step) for(i=0; i<size; i=i+1) in_state[i] = 0; generate i (0, size-1) begin // I(in[i]) <+ C_IN*ddt(V(in[i])); @(cross(V(in[i]) - vth)) begin // Hack to workaround spice problem for(j=0; j<size; j=j+1) in_state[j] = V(in[j]) > vth; // Hack to workaround spice problem End out_state = 1; for (k=0; k<size; k=k+1) begin if (!(out_state && in_state[k])) out_state = 0; end if (out_state) vout = vout_low; // Inversion else vout = vout_high; end end V(sw) <+ transition(vout,tdelay,trise,tfall); end endmodule // ////////////////////////////////////////////////////////////////////////
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