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The Designer's Guide Community Forum › Design Languages › Verilog-AMS › Adding phase noise in the VCO model

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Adding phase noise in the VCO model (Read 2054 times)

Amit Singh New Member Offline Posts: 6	Adding phase noise in the VCO model Mar 15^th, 2007, 7:08am Hi, I am simulating a PLL and using verilog model of VCO. How can i include phase noise of VCO in to this model ? Thanks for your help, Amit
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Ken Kundert Global Moderator Offline Posts: 2386 Silicon Valley	Re: Adding phase noise in the VCO model Reply #1 - Mar 15^th, 2007, 1:27pm I suggest you read "Predicting the phase noise and jitter of PLL-based frequency synthesizers", which can be found on www.designers-guide.org/Analysis. -Ken
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