zhangjerome
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I am now designing a CML D latch biased with cascoded current source. With transient simulation, the drain current and source current of the common-gate transistor in the current source differs from each other by about 400uA. I checked the node current and found out that the current goes to B node.
The substrate of the transistor is grounded, and the transistor is in active region. I totally have no idea how this coulde happen.
Is this a model problem or simulation problem? Or there is something wrong with my circuit??
Thanks, bow~~
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