Hi,

I'm putting together a PLL  model of an N-integer PLL.  I have been unable to clamp the error voltage
going to the VCO with the pfd structure that I have?  Does anyone have any suggestions.  I am really new to
this modeling so most of this is taken from This Designer's guide site.

By the way this PLL needs to lock 180 degrees out of phase with input ref clk, but that works fine

Loop filer is also include..

Help..



module pfd_cp(out,ref,fb);

input ref, fb;
inout out;
electrical ref, fb,out;

parameter real Iout=100u;
parameter integer dir=1 from [-1:1] exclude 0;
parameter real Vlo=0, Vhi=1.2;
parameter real tt=1n from (0:inf);
parameter real ttol=1p from (0:inf);

real state,sign;
real dump_current;

analog begin
       @(cross(V(ref)-(Vhi+Vlo)/2, dir,ttol)) begin
         if(state>-1) state = state -1;
       end
       @(cross(V(fb)-(Vhi+Vlo)/2, -1, ttol)) begin
         if(state<1) state=state+1;
       end


// something like this ?
       dump_current=1;
       if (V(out) > Vhi)
               if ( state>-1 ) dump_current=0;
       if (V(out) < Vlo)
               if ( state<1  ) dump_current=0;

       I(out) <+ transition(dump_current*Iout*state, 0, tt);
end

endmodule



loop filer
module loopFilter_20db (in, out, gnd);
inout  in, out, gnd;
electrical in, out, gnd;

parameter real c1 = 0.24p from (0:inf);
parameter real c2 = 2.36p from (0:inf);
parameter real c3 = 0.05p from (0:inf);
parameter real r1 = 22515.40 from (0:inf);
parameter real r2 = 7505.13 from (0:inf);

electrical nc2;

capacitor #(.c(c1)) c1(in,gnd);

resistor #(.r(r2)) r2(in,nc2);
capacitor #(.c(c2)) c2(nc2,gnd);

resistor #(.r(r1)) r1(in,out);
capacitor #(.c(c3)) c3(out,gnd);

endmodule