senyou78
New Member
Offline
Posts: 9
germany
|
hi,
I am coding in VerilogA and I want switched capacitor model for resistor. But capacitor is behaving very ackwardly. And when i simulate then i get zero diagonal found Jacobian. Codes for switch and capacitor are geiven . Used software is cadence.
// VerilogA switch, veriloga
`include "constants.vams" `include "disciplines.vams"
module switch(pc,nc,p,c); input pc , nc; output p , c; electrical pc,nc,p,n; parameter real vth =0.6; parameter real dir = +1 from [-1:1] exclude 0; analog begin
@(cross(V(pc,nc)-vth, dir)); if(V(pc,nc) > vth) V(p,n) <+ 0; else I(p,n) <+ 0;
end
endmodule
/ VerilogA for Ca, veriloga
`include "constants.vams" `include "disciplines.vams"
module C(p, n);
inout p, n; electrical p, n; parameter real c=1 from (0:inf);
analog begin I(p,n) <+ c*ddt(V(p,n)); end endmodule
help would be highly appreciated.
|