Hi, I'm pretty new to Verilog-AMS and was wondering how I can get a reasonable model of a cascode current source.  I'd like to be able to have a triode and saturated mode, and a suitable output resistance.  I'm not trying to re-invent the wheel here, so if a good model exists, please let me know!  Thanks!

I'm curious why you wouldn't use a Spice model. If you're using the cascode in a self-referenced source, then it makes sense to model the start-up circuit behaviorally. But I'd still keep the cascode in Spice.

M.G.Rajan
www.eecalc.com

How about using the schematics in spice for normal mode of simulation and
using the tool like AMS designer to compile it , when the faster simulation
is required for the analog blocks?

Regards,
Krishna

Not sure what Krishnap was trying to say, but a transistor level design won't run any quicker in AMS Designer than it would in spectre (unless you're using Ultrasim as the analog solver). If the solver is the same, it will take a similar time.

The benefit of AMS Designer is when you have mixed-signal models in Verilog-AMS or VHDL-AMS, and pure digital parts in Verilog or VHDL. Then you don't need to simulate everything at transistor level any more...

Regards,

Andrew.

Actually Cadence has a tool "DCM" which effectively does this. It has a library of templates (which you can extend yourself using OpenDCM) and it characterises the circuit using simulation and fits a behavioural model in Verilog-A/Verilog-AMS to the measured circuit behaviour...

In IC5141 this is an extension to the Virtuoso Specification Driven Environment (sometimes known historically as "Aptivia"), and in IC61X it is part of Virtuoso Analog Design Environment GXL.

Regards,

Andrew.