In my veriloga cell, the syntax is fine but things mysteriously break when I attempt to simulate.

ERROR: netlister : terminal of instance X in cell B, view veriloga : not found on master

My code seems pretty straightforward to me.  It seems like there is a CAD tool problem more than a veriloga code problem...

module x( sig1, sig2 );
 input sig1;
 output sig2;
 electrical sig1, sig2;

 mymod X( sig1, sig2 )
endmodule

In the real code, the veriloga ports and definitions were generated automatically from the symbol view.  The ports of mymod are inouts.

This one is making me pull my hair out!  

Oh, don't scrutinize the syntax too carefully, just trying to convey the idea.

It turns out that it would break or not depending on what order I instantiated the instances.  This makes no sense from a code point-of-view.  Tools misbehave.

Sorry, I should have qualified that these keywords are reserved for the digital part of Verilog-AMS or in Verilog-HDL. The yare reserved as binay/octal/hex digit specification to convey that the value is unknown. Try just changing these names.