ywguo wrote on Apr 28th, 2007, 11:55pm:Hi, mosman,
You'd better think over some techniques that reduce the simulation time accordint to your specific circuit. I think that depends on your design.
However, there are some general guide, too.
- Only save the voltages/currents that you want to measure.
- Replace some complex circuit with ideal model like verilog-a model.
- Simulate the related circuit only, NOT the whole chip, for some specs if possible.
Yawei
Thanks Yawei very much!
1. yes saving less number of v/I will save time.
2&3. i am afraid that verilog-a model should use at the strat of project. when in the end of one project we want to verify all specs. so we should combine one block with others. it will increase the simulation time.
recently i learned a method to simulate some large circuits which consist of feedback loop. the new method is named open simulation (maybe :( ) this method is to open the loop of the circuit to verify some specs such as over voltage, over current, and so on. due to no feedback the method save much time compared with the old closed verify method. but i think acctually this circuit is running at open situation. is it different with the normal situation? under such case the result is right or wrong? can i trust the results?
do anyone know more infomation about this method? and do you think about this method?