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Chipmuenk

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Germany

VHDL-AMS and VHDL cellviews in AMS Designer
May 14^th, 2007, 6:47am

Hello,

after a few digital years I'm back to MS again. This time I'm trying to verify a small a, big D chip using AMS Designer. The analog blocks of the chip are modeled using VHDL-AMS. For performance reasons I also need a purely digital model of the analog blocks that will be used for extensive simulation of the digital part. These digital models provide a pin-true, basic functional description and have to be verified against the VHDL-AMS models.

Here comes the tricky question:

How do I create / handle VHDL- and VHDLAMS cellviews for the same cell at the same time? The standard "cellview-from-cellview" generation creates a view "entity" for both VHDL and VHDLAMS, overwriting an existing entity. Changing the view name to be created into e.g. "entity_ams" results in an architecture with the name entity_ams.

Ideas, anyone?

Cheers,

Chris

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Ankur.Chaplot

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Posts: 2
Noida,India

Re: VHDL-AMS and VHDL cellviews in AMS Designer
Reply #1 - Jun 11^th, 2008, 2:39am

Hi Chris,
I fail to understand why the entity for vhdl and vhdl-ams model should be different. In my opinion, the architectures should be different.
Please provide the exact use model to comprehend the problem.
Cheers
Ankur C
Chipmuenk wrote on May 14^th, 2007, 6:47am:

Hello,

after a few digital years I'm back to MS again. This time I'm trying to verify a small a, big D chip using AMS Designer. The analog blocks of the chip are modeled using VHDL-AMS. For performance reasons I also need a purely digital model of the analog blocks that will be used for extensive simulation of the digital part. These digital models provide a pin-true, basic functional description and have to be verified against the VHDL-AMS models.

Here comes the tricky question:

How do I create / handle VHDL- and VHDLAMS cellviews for the same cell at the same time? The standard "cellview-from-cellview" generation creates a view "entity" for both VHDL and VHDLAMS, overwriting an existing entity. Changing the view name to be created into e.g. "entity_ams" results in an architecture with the name entity_ams.

Ideas, anyone?

Cheers,

Chris

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jbdavid Community Fellow Offline Posts: 378 Silicon Valley	Re: VHDL-AMS and VHDL cellviews in AMS Designer Reply #2 - Aug 27^th, 2008, 1:26am drop the VHDL and use Verilog? sorry!
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