The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Jul 22nd, 2024, 8:21pm
Pages: 1
Send Topic Print
Spectre - Time consumption of the topology check (Read 5217 times)
haikom
Junior Member
**
Offline



Posts: 17
Germany
Spectre - Time consumption of the topology check
May 30th, 2007, 1:51pm
 
Hi,

I'm doing SPICE-level simulation of mixed signal circuits. One simulation takes 1/2 hour. But when I have a look at the file spectre.out, the computing time is only 5 to 7 minutes. So what takes the rest of the time? Saving the data at the harddisk, IDLE states of the spectre-process, or the topology check which is done before the simulation.
I assume that the topology check takes the rest of the time. Is this correct?
If yes, can I save this information to do this process only one time?

As I know during the topology check the schematic is scanned for floting nodes and gmin or cmin are added. So maybe this process has to be done before every simulation?
I'm happy about any comment  :)

Kind regards,
haikom
Back to top
 
 
View Profile haikomo   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2386
Silicon Valley
Re: Spectre - Time consumption of the topology che
Reply #1 - May 30th, 2007, 10:46pm
 
In Spectre, the topology check is very fast. In a half hour simulation it should take no more than a second or two.

-Ken
Back to top
 
 
View Profile WWW   IP Logged
didac
Senior Member
****
Offline

There's a million
ways to see the
things in life

Posts: 247
manresa,spain
Re: Spectre - Time consumption of the topology che
Reply #2 - May 30th, 2007, 11:30pm
 
Are you running your simulation in a shared computer?If it's linux base I think that the computing time is the real time that the process had acceded to the CPU while if there many users you will see this kind of slow-down because they also access to the CPU thus increasing your total simulation time.
Back to top
 
 
View Profile WWW   IP Logged
haikom
Junior Member
**
Offline



Posts: 17
Germany
Re: Spectre - Time consumption of the topology che
Reply #3 - May 31st, 2007, 4:20am
 
Hi,

thanks for your answers. I'm still wondering about the time consumption. Here are more details about the simulation:
Parameter topcheck = full
Total analysis time: 25min
  - Simulation preprocessing 20min (all processes after "Simulating input.scs" til "Transient Analysis..." including topology check)
  - Transient analysis 5min (Initial condition solution 78sec, Intrinsic tran analysis 240sec)
Parameter topcheck = no
Total analysis time: 50min
  - Simulation proprocessing 37min
  - Transient analysis 13min

Ken, you said the topology check takes only a few seconds. But what is spectre doing 20min / 37min before the transient analysis? There are a lot of warnings like "rs has been deleted because its value was smaller then 'minr' ". Is this done during the topology check?

Kind regards,
haikom
Back to top
 
 
View Profile haikomo   IP Logged
ywguo
Community Fellow
*****
Offline



Posts: 943
Shanghai, PRC
Re: Spectre - Time consumption of the topology che
Reply #4 - Jun 3rd, 2007, 11:22pm
 
Hi, Haikom,

Are you running a post-layout simulation?

Quote:
There are a lot of warnings like "rs has been deleted because its value was smaller then 'minr' ".

It looks that the netlist has many many very small resistors. I guess the netlist file size is very large because it contains all parasitics in layout. So it is very clear that the total analysis time increase to 50min when parameter topcheck=no. I guess that there are no warnings like "rs has been deleted because its value was smaller than 'minr' ".


Best regards,
Yawei
Back to top
 
 
View Profile   IP Logged
Andrew Beckett
Senior Fellow
******
Offline

Life, don't talk to
me about Life...

Posts: 1742
Bracknell, UK
Re: Spectre - Time consumption of the topology che
Reply #5 - Jun 4th, 2007, 12:55pm
 
It might  be useful to give a bigger segment of the spectre.out file, including the circuit inventory, and so on. Perhaps its taking a long time to do the dc solution? It's very hard to tell from a small snapshot (I assume that was two snapshots from different simulations? It wasn't very clear).

Regards,

Andrew.
Back to top
 
 
View Profile WWW   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.