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deep probe (Read 3416 times)

Venkateshr Junior Member Offline Posts: 10 Bangalore	deep probe May 31^st, 2007, 4:17am how to probe a net which is deep inside the circuit ? I dont want to bring that to top level.All I can give is the full net name then my verilog-a block should make that available in top level. this is similar to deepprobe block
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rajdeep Senior Member Offline Posts: 220 UK	Re: deep probe Reply #1 - May 31^st, 2007, 11:12am I think try to use hierarchical names. To probe a net n1 which is in module A, and module A is in module Top use Top.A.n1 Rajdeep
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Venkateshr Junior Member Offline Posts: 10 Bangalore	Re: deep probe Reply #2 - May 31^st, 2007, 9:48pm hierarchial addressing is ok but whether that net is accessible in the top level. I don't know
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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: deep probe Reply #3 - Jun 1^st, 2007, 9:09am I thought that you could always access something if you had its full hierarchical name.
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Venkateshr Junior Member Offline Posts: 10 Bangalore	Re: deep probe Reply #4 - Jun 1^st, 2007, 11:07pm thank you. I will try that.
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