Hi, All,
I found a problem in the simulation of a Delta-Sigma fractional-N PLL by cadence AMS designer. I construct the PLL by the blocks in different forms:
(1) PFD, charge pump and loop filter: Spectre netlist
(2) VCO: verilog-A model
(3) Feedback divider and Delta-Sigma modulator: Verilog-HDL
The Delta-Sigma modulator output a divider ratio at each reference clock, and the long term average is the wanted fractional divider ratio. But in the simulation, I can't see the "averaging" effect. The PLL works as a integer-N PLL with different divider ratio at each reference clock. I also use the FFT to observe the spectrum of the output, but still hard to find out a major tone.
Is the AMS feasible for such simulation. Please give me some advise about this issue.

Thanks and Best Regards.

Leon