Hi,

I have a Two phase Voltage Doubler (TPVD) in my design. There are transient bulk/nwell currents when the clocks rise/fall together. Basically its the capactive coupling i.e. Cgb, Cdb. The size of the transistors is quite large becuase I intend to minimize the static losses.

Are there ways to reduce this transient bulk/nwell currents? (The bulk drain junction is reverse biased)


Hi, Faisal,

  In my option, the switching noise can not be avoided in Voltage doubler. There are some ways to reduce them:

1) make an auxliary pmos in parallel with the main out power pmos to supply the nwell baising, such that the switching noise due to paracitic cap Cds coupling can be reduced. This idea can be found in the paper:

P. Favrat, P. Deval, and M.J. Declercq, "A high efficiency CMOS voltage doubler," IEEE J of Solid-States Ckt., March 1998, pp.410-and Fig. 15 respectively. 416.

2) There are undesired reversion current loss during the transient of the clocks or even in the overlapping period of the clocks.  These could be elimited by properly arrange the sequence of the gate control signals. The detailed infos can be found in the paper:

F. Su, W.H. Ki and C.Y. Tsui, "High efficiency cross-coupled doubler with no reversion loss," IEEE Int'l. Symp. on Ckts. & Sys., Koa, Greece, pp.2761–2764, May 2006.

3) The switching slope of the power switches' gate terminals should be slowed down to further degrade the switching noise. A simple method can be found in the paper:

H. Lee and P. Mok, "Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doubler", IEEE Journal of Solid-States Ckt., May 2005, pp.1136-1146.

Hope these infos helpful.

Feng