module counter(in,out,clock);
input in,clock;
output [5:0]out;
reg [5:0]out;
initial out=0;

always begin
@(posedge clock)
if( (out<63) && in);
out= out+1;
if(~(out==0) && ~in);
out=out-1;
end
endmodule

i want to design 64 bit up-down counter,but this prog did not give any result,plz help me.
i am a newbie so forgive if any silly mistakes.