hai,
I am trying to model an oscillator.following is the code,please tell me if i am right also is there any limitation for it....if so please specify.because when i introduce it in acircuit which has clocked comparators and the output of the oscillator forms the clock ,i am getting wrong results

// VerilogA for san, vericomp, veriloga

`include "constants.vams"
`include "disciplines.vams"

module oscf(out, cont);
input cont;
output out ;
electrical out, cont ;
parameter real vl=0;            // high output voltage
parameter real vh=1.5;            // low output voltage
//parameter real tt=0.01/freq from (0:inf);// transition time //of output
parameter real vtrans = 0.1 ;
integer n ;
real next ;
real freq ;
analog begin

@(initial_step) begin
     freq = 500000 ;
     next = 0.5/freq + $abstime;
       
   end
@(timer(next)) begin
     n = !n ;
     next = next + 0.5/freq ;
   end
   V(out) <+ transition(n ? vl : vh, 0, 100p);    
@(cross(V(out) - vtrans, 1 ))
if(V(cont) > 1000u) begin
freq =  freq - 50000;
end
else if  (V(cont) < 1000u) begin
freq =  freq + 50000;
end
else begin
freq =  freq + 50000;
end

end


endmodule