All,

I am starting to write verilogAMS test benches to verify the functionality of my schematics and models. I want to reuse my code so I am trying to fold them into a task. However, I am running into problems when I try to pass a analog signal to the task. For example I have a task call e_20MHz and I pass it an "analog" port:

e_20MHz(I0.X1);

My task is define:

  task e_20MHz;
     input in1;
     real  in1;

     real         tp0;
     real         tp1;
     real         tp_val;
     begin
        tp0 = V(in1);
        #25 tp1 = V(in1);
        tp_val = (tp0 - tp1)/2.0;
        $fdisplay(d_fd,"%7.3f\tE@20MHz XO\t%5.2g", $abstime*1e6, tp_val);        
     end
  endtask // e_20MHz


When I run, I get this error:

verilog.vams
        tp0 = V(in1);
                  |
ncvlog: *E,EXPBON (/xxx/verilog.vams,87|19):  Expecting only branch or node type arguments [5.2(AMSLRM)].
        #25 tp1 = V(in1);
                      |
ncvlog: *E,EXPBON (/xxx/verilog.vams,88|23):  Expecting only branch or node type arguments [5.2(AMSLRM)].
       module xxx.v_XO2:verilogams
               errors: 2, warnings: 0


Any ideas?

ncvlog did not like that at all:



     electrical in1;
                  |
ncvlog: *E,MISEXX (/xxx/verilog.vams,80|19): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].


jr