Iam just tring to implement the adc example in the 'designers guide to verilog ams'
This is part of the code Iam using....

parameter integer bits = 8 from [1:24];      
genvar i;
integer g;

analog begin
     @(cross(V(clk)-thresh,+1) or initial_step) begin
     sample =V(in);
     midpoint = fullscale/2.0;
     for (g=bits-1; g>=0; g=g-1)begin
           if (sample>midpoint) begin
             result[g]=vdd;
             sample = sample-midpoint;
           end
           else begin
             result[g]=0.0;
           end
           sample =2.0*sample;
     end
     end //end cross

     for (i=0;i<bits; i= i+1)
     begin
     V(out[i])<+transition(result[i],td,tt);
     end
     end //analog end

when I try simulating this using  AMS (Analog design environment XL) this is the error I get....
Error found by spectre.
   Problem found in instance `pip_adc_top.I9' of module `pip_adc'
     for (i=0;i<bits; i= i+1)
               |
ncelab: *E,SYERROR (/home/mjayara/test/pip_adc_top/adexl/results/data/Interactive.44/1/test:pip_adc
_top:1/netlist/ihnl/test/pip_adc/verilogams/verilog.vams,39|11): In for-loop control, genvar expression can only consists of integer constant or other unrolled genvar variables expression.

Could someone help me out.... As far as I see it Iam using integer constants in the genvar expression......