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[q] transient noise in Verilog-A (Read 4769 times)
Renekim
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[q] transient noise in Verilog-A
Sep 05th, 2007, 7:55pm
 
Dear all,

  I'd like to simulate transient noise in hspice simulation.
  So first i thought of using verilog-a $rdist_normal function.
  But since hspice will run with variable step.
  So strictly speaking, the values generated by $rdist_normal will not be
  placed uniformly in time. So I think this means autocorrelation will not be delta.
  I think unless I fix the simulation time step..this will not be white noise.
  Am I right?


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Geoffrey_Coram
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Re: [q] transient noise in Verilog-A
Reply #1 - Sep 7th, 2007, 6:09am
 
You are correct.  I think you have to force HSpice to take tiny timesteps so that it generates samples at a bandwidth higher than the highest frequency of interest to your circuit.

Spectre and Eldo support transient noise natively; will HSpice be joining them soon?
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If at first you do succeed, STOP, raise your standards, and stop wasting your time.
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Ken Kundert
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Re: [q] transient noise in Verilog-A
Reply #2 - Sep 7th, 2007, 8:00am
 
All simulators have the same issue, it is just that Spectre and Eldo have automated things a bit. You can solve your variable sample rate problem by only updating the random noise at fixed rate. You can use the timer function to help with that. Then you just have to choose a rate that is sufficiently high.

In general, transient noise is difficult and error prone. Do you have access to an RF simulator that would allow you to do an RF noise analysis?

-Ken
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Marq Kole
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Hmmm. That's
weird...

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Re: [q] transient noise in Verilog-A
Reply #3 - Sep 26th, 2007, 1:57am
 
So using timer events it can be done correctly in Verilog-A. It will give a tremendously slow simulation, though.

Marq
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rajdeep
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Re: [q] transient noise in Verilog-A
Reply #4 - Sep 26th, 2007, 3:01am
 
I've got a question somewhat related to this, so thought to put it here....
           
                    Is there a way to throw an event at every simulation time point?

     This will be very helpful in some cases and we can avoid using 'timer' type of things, which slow down the simulation. For example, if I want to monitor that the current flowing through a branch is monotonically increasing, I have to sample the current at a certain rate and measure the difference between the two consecutive sample points to check whether the difference is nonnegative or not (ddt does create convergence issues!!). But this slows down the simulation. A better way would be to use a variable sampling clock to tick at the rate of the simulator.
Then I can use the cross construct to trigger the monitor.
                      Is it possible in cadence spectre, spectreVerilog or any other simulator??

Rajdeep
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Ken Kundert
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Re: [q] transient noise in Verilog-A
Reply #5 - Sep 26th, 2007, 11:18am
 
The analog block is evaluated on every analog time point, so to get what you ask for, write the code outside any event statements.

-Ken
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