Hy
I have two blokcs , one block it is made in verilog and had an digital output , this digital output enter in a block where it is conected to an electrical input. When I made the simulation i dont receive any error but when i have a transition on the digital signal , the electrical signal dont have any transition , remains in 0V.
Do you know what can be the problem .For my models i using CADENCE?

AL