hi all, i am a student in electronics. This semester i have two assignment questions where i do not have any clue to solve it. Try to put the questions here and hope can get some guides from you
question 1: a) sketch a dual-edge triggered register designed using static Master-slave latches 2) sketch a dual-edge triggered register designed using C2MOS register
question 2: design a cmos D FF with negative setup time (NSFF)