hi,all;
     i am designing a sigma-delta ADC,when i want to model a full differential opamp block,then i can find the parameter of opamp how to influence the performance of modulator,but i can not built a full differential opamp in veriloga,and the opamp can inculde these parameter of slew rate,gain,frequency-gain,rout and so on!
    i have modeled a opamp reference to opamp in ahdlLib in cadence,but i can not work at all.
   would you give me some advice?or give some example?thank you in advance!

There are a good number of legacy examples in the forum here.. Use the search function..
Thats why we should have a wiki.. eh?