Hi all,

I wish to implement noise sources into a RF transistor model. I managed to implement the drain noise current using verilog A with the white noise command. But i am unable to implement the same way for the induced gate noise.

The induced gate noise that i wish to implement includes a resistor in series with a capacitor. How to write it in verilog A to describe such circuit? Thanks.


regds,
humble_student

Dear Sir,

Thanks for your informations. I am trying to understand what you have written in your verilog program of induced gate noise. but as there is no comments in the program, i am afraid that i may interpret wrongly. any other document i can read about your implementation?

Thanks.

Also if possible, may i know how do you check your simulated induced gate noise with your extracted induced gate noise current?

Thanks.

Colin McAndrew and I wrote a paper on correlated noise modeling:
http://www.nsti.org/procs/Nanotech2005WCM/1/T46.03