Hi,
I have ever seen the IP of I/O standcell for 0.13um, 90nm and 65nm CMOS process. The above IPs used in the MCU chips which have criticl requirements on the di/dt noise. But I noticed that for the I/O interface buffer which dominate the di/dt noise have seldom used the CSL(current steering logic) buffer as I/O.They always used the slope limited technique to reduce the di/dt noise.

I wonder why the CSL buffer is always used as internal logic and not used as I/O buffer? Is it because of its drive capability?

Thanks in advance

a follow-on to ywguos answer,
A lot of times, the I/O interface does not have a constant current flowing, meaning during static phases there is no bias current.  If you tried to use CSL in this I/O configuration it would actually start to look like nothing more than a fancy inverter because there is no bias current flowing that would keep the devices in saturation, rather the CSL buffer would quickly fall out of saturation/biasing between transitions.  

Granted this is not for every MPU interface as some of the interfaces do have termination impedances which could be used for biasing currents upon which the CSL buffer would depend, but it becomes more complex.

You could also add On-die terminations strictly to allow the use of a CSL buffer but then you start to burn a lot more static power in your I/Os that an inverter would not be burning, so you have to consider power consumption to.  A lot of CSL type interfaces do burn significantly more power than a standard inverter buffer.

Something else to think about.
Thanks,
Stephen
SRF Technologies