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The Designer's Guide Community Forum › Simulators › Circuit Simulators › use of # in verilog modules in spectreVerilog
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use of # in verilog modules in spectreVerilog (Read 1525 times)
rajdeep
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use of # in verilog modules in spectreVerilog
Oct 08th, 2007, 8:33am  
Hi all,

Is it  meaningful to use #50 (delay statements) in a verilog module while simualting with  spectreVerilog?
How can we specify the time step (using `timescale) when simualting with spectreVerilog when  the timestep for
simulation is decided by the simulator?

Can anyone explain plz?

rajdeep
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