Hi,


I hope that the code is "synthesizable".
I think I have one last problem:

I was using monitor statement for debugging purpose (which will not be a part of my synthesized code)

I am getting garbage values for my variables(in1,out1,out2,temp_u1,temp_u0). However, when I do a mouse over the variables, the value is correct. Could anyone please help ?

Code:
-------

module conencoder (out1,out2,in1,clock,reset,first);
output out1,out2;
input in1,clock,reset,first;
reg u0,u1,u2,temp_u0,temp_u1,temp_u2;
reg out1,out2;

always @(first)
begin
out1 <= 1'b0;
out2 <= 1'b0;
u0 <= 1'b0;
u1 <= 1'b0;
u2 <= 1'b0;
temp_u0 <= 1'b0;
temp_u1 <= 1'b0;
temp_u2 <= 1'b0;

end

always @(clock)
begin
if (reset)
begin
u2 <= temp_u1;
u1 <= temp_u0;
u0 <= in1 ;

$monitor($time,"u2 = %b ","u1 = %b ", "u0 = %b ",u2,u1,u0);

end

else if (!reset)
begin
out1 <= (u2 ^ u1 ^ u0);
out2 <= (u2 ^ u0);
temp_u1 <= u1 ;
temp_u0 <= u0 ;

// taking two lines due to forum post space formatting. It is one line.

$monitor($time,"input = %b ", "out1 = %b ", "out2 = %b ","temp_u1 = %b ", "temp_u0 = %b ",in1,out1,out2,temp_u1,temp_u0);


end
end

endmodule


------------------------------------

Testbench:

module testbench ;
reg first,clock,reset,in1 = 1'b0;


conencoder r1(out1,out2,in1,clock,reset,first);


always
begin
#1 first = 1'b1 ;
#1 reset = 1'b1 ;
#1 in1 = 1'b1;
#1 clock = 1'b1 ;
#1 reset = 1'b0;
#1 clock = 1'b0;
//follow this sequence
#1 reset = 1'b1 ;
#1 in1 = 1'b1;
#1 clock = 1'b1 ;
#1 reset = 1'b0;
#1 clock = 1'b0;
#1 reset = 1'b1 ;
#1 in1 = 1'b1;
#1 clock = 1'b1 ;
#1 reset = 1'b0;
#1 clock = 1'b0;
#1 reset = 1'b1 ;
#1 in1 = 1'b0;
#1 clock = 1'b1 ;
#1 reset = 1'b0;
#1 clock = 1'b0;
#1 reset = 1'b1 ;
#1 in1 = 1'b1;
#1 clock = 1'b1 ;
#1 reset = 1'b0;
#1 clock = 1'b0;
#1 reset = 1'b1 ;

end

initial
$monitor($time,in1,out1,out2);

endmodule

------------------------------


I think I am doing some mistakes in either displaying or formatting my output.


Thanks in advance.