I'm trying to instantiate a model in Verilog-A where the cell name is different than the model name.

For example:
Library Name: lib
Cell Name: foundry_cell
View Name: symbol
Under CDF parameter
Model name: model_of_cell

In Verilog-A, I tried:
foundry_cell #(.param1...) (.node1(x)...);

When doing this the elaborator says "Cannot find any unit under lib:foundry_cell:symbol in the design libraries".  This makes sense as it has no way of knowing the mapping from foundry_cell to model_of_cell.  I also tried:

model_of_cell #(.param1...)(.node1(x)...);

This doesn't work, because there is no cell view called "model of cell"

Is there a way I can specify the model name when I instantiate "foundry_cell" in Verilog-A?  Is there a parameter for model name that I can use?

-I Verify