The high level benefits from a digital subsampling architecture include
1. It is closer to a "digital" circuit architecture. This enables easier design flows in digital processes.
2. Flexibiltiy to reconfigure the "digital" architecture as needed for different standards. Traditional analog/RF designs sometimes run into difficulty at baseband because of the different analog channel filtering requirements. This flexibility has been noted by a few as an enabling technology for software defined receivers.
3. In the past it was believed that sampling receivers would always have unacceptable NF due to noise folding, but the problem has been partially solved by incorporating FIR and IIR filter functions into the subsampling functions of the receiver.
4. Linearity is still an issue. You have to have an LNA and front-end amp before the subsampler just like in a LNA downconverter design. I have not seen a detailed discussion of linearity within the subsampler itself.
Here are a couple of good technical references on the technology.
A. A. Abidi, "The Path to the Software-Defined Radio Receiver," IEEE J. Solid-State Circuits, vol. 42, no. 5, 2007, pp. 954-966.
R. Bagheri, A. Mirzaei, S. Chehrazi, M. E. Heidari, M. Lee, M. Mikhemar, W. Tang, and A. A. Abidi, "An 800-MHz - 6-GHz Software-Defined Wireless Receiver in 90-nm CMOS," IEEE J. Solid-State Circuits, vol. 41, no. 12, 2006, pp. 2860-2876.
K. Muhammad, Y.-C. Ho, T. L. Mayhugh, Jr., C.-M. Hung, T. Jung, I. Elahi, C. Lin, I. Deng, C. Fernando, J. L. Wallberg, S. K. Vemulapalli, S. Larson, T. Murphy, D. Leipold, P. Cruise, J. Jaehnig, M.-C. Lee, R. B. Staszewski, R. Staszewski, and K. Maggio, "The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process," IEEE J. Solid-State Circuits, vol. 41, no. 8, 2006, pp. 1772-1783.
S. Karvonen, T. A. D. Riley, S. Kurtti, and J. Kostamovaara, "A quadrature charge-domain sampler with embedded FIR and IIR filtering functions," IEEE J. Solid-State Circuits, vol. 41, no. 2, 2006, pp. 507-515.
D. Jakonis, K. Folkesson, J. Dbrowski, P. Eriksson, and C. Svensson, "A 2.4-GHz RF sampling receiver front-end in 0.18-/spl mu/m CMOS," IEEE J. Solid-State Circuits, vol. 40, no. 6, 2005, pp. 1265-1277.
J.-F. Luy, T. Mueller, T. Mack, and A. Terzis, "Configurable RF receiver architectures," IEEE Microwave Magazine, vol. 5, no. 1, 2004, pp. 75-82.
R. B. Staszewski, J. L. Wallberg, S. Rezeq, C.-M. Hung, O. E. Eliezer, S. K. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M.-C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, "All-digital PLL and transmitter for mobile phones," IEEE J. Solid-State Circuits, vol. 40, no. 12, 2005, pp. 2469-2482.
K. Muhammad, R. B. Staszewski, and D. Leipold, "Digital RF processing: toward low-cost reconfigurable radios," IEEE Communications Magazine, vol. 43, no. 8, 2005, pp. 105-113.