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May 19th, 2024, 6:29pm
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DAC SFDR measurement in Tanner (Read 2608 times)
arjunpcet
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DAC SFDR measurement in Tanner
May 08th, 2008, 5:46pm
 
hi all....I have designed a 10 bit 100 MHz current steering DAC in Tanner EDA.... To measure SFDR i need to use an ideal ADC at the dac input.....But the problem is that Tanner doesnt support verilog A models for ideal ADC...and i cant find a spice netlist for an ideal 10 bit ADC....so plz do help me....
                                                                                                     thanks in advance
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patrick
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Re: DAC SFDR measurement in Tanner
Reply #1 - May 8th, 2008, 10:10pm
 
Version 13.0 supports Verilog-A (LRM 2.2).

Patrick
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