ssdfz wrote on May 12th, 2008, 10:55pm:Hello Everyone:
By browsing through this forum, I realize that there are many true expert of VerilogA. I was hesitant about posting my problem as I am afraid it would be too trivial for you. But this issue has been really bothering me for couple of days… I am trying to model the gate capacitance of a mosfet; assuming the Cg = Cgoff when Vgs < Vth and Cg = Cgsat when Vgs > Vth. Below is my code. It really just needs the first two inputs and the latter three are just for debugging. The code works okay until the line above the one with (***). Without a transition for q, it seems that the simulator will complain. I added the transition filter hoping to smooth the transition. However, it turns out that V(out) is just a flat line whereas V(qout) is switching. Could anyone give your valuable suggestion? To me it seems that the transition filter is just not working properly here.
Second question: the simulation I am using is hspice. When I switched to HSIM, it always complain with the syntax of @(above (v - vth) ). Anyone knows the reason?
2nd first: "above" is a relatively new addition to the language, from LRM 2.2.
Back to your main question: I surely would expect a simulator to complain if the charge is discontinuous as a function of voltage. You should try to write some equation for "q" (not c! -- though you've got a linear cap, so that's not the issue here) that is continuous in voltage, and one that doesn't use events but is valid for all v.
In your current system, for v==vth - epsilon, you have q = cgoff * vth; for v==vth+epsilon, you have q = cgsat * vth. So, even for a very slow ramp of "v" across vth, you have a delta-q (I = dq/dt) of (cgsat - cgoff) * vth, which makes for a huge spike in current.