ssdfz
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Hi All:
When I run transient simulation for each individual verilogA block, the simulation time is pretty short (say around 0.01sec ~ 0.1sec for 3us transient). however, when I connect about 30 blocks together (most of them are verilogA model of digital gates, together with other models such as res, cap, comparator, switch), the total simulation time is about 40 sec for 3us transient. however, the full spice model will conclude within 10 sec. By looking at the output log file, it seems that verilogA model simulation takes much more iterations. I feel something wrong among the interface of blocks, but dont have much clue on what direction I need to debug. I tried to take care of discontinuity issue by feeding piece-linear output with transition filter, so the output didnt complain/warn about that. As writing this post, I just have two ideas: 1. add large parallel resistance with capacitor, so that the node connecting the cap has DC ground; 2. change the discipline from electrical to voltage. But honestly I don't understand what's going wrong.
Could you please give some suggestions? I know it would be hard without seeing the code...
Thank you in advance Erik
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