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Parameteric sweep of Verilog modules (Read 3044 times)
mattlohry
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Parameteric sweep of Verilog modules
Jun 04th, 2008, 3:07pm  
I was wondering if it is possible to sweep a parameter defined in a Verilog module via the parameteric sweep tool of ADE when using SpectreVerilog or UltraSimVerilog?

If not, is there any other way to get a similar result by a different approach?

Thanks for the assistance.
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jbdavid
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Re: Parameteric sweep of Verilog modules
Reply #1 - Oct 9th, 2008, 6:25pm  
I'd use AMS if I were you..
if you set the instance parameter value to a DESIGN VAR (one of those ADE things) then you can sweep it..
as an example look at the bmslib busset8 verilogams model..
its designed exactly for this purpose..
(BTW bmslib is located in the same cadence install directory as ahdlLib)
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jbd
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jbdavid
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