i want to realize  a time-varying sine signal which amplitude  changes linearity  with time，expression as vamp=k×t+vamp₀.where k is a coefficient and vamp₀ is an initial value。
how to realize it inverilog-a？
thank you in advanced！

first ,thank you for your attention.
i realize in follow code：
//a timing-vary
`include "disciplines.vams"
`include "constants.vams"

module linamp(n1,n2);
      electrical n1,n2;
      real vamp;
      parameter real freq = 1.25e9 from (0:inf);
      parameter real k=100000 from (0:inf);
      analog begin
            vamp =k*$abstime;
           V(n2,n1) <+ vamp * sin(2 * `M_PI * freq * $abstime);
      end
endmodule