Hello,

Trying to "Design Prep" of very simple design that consisists of one cell - VHDL-AMS model of sinus generator, tool outputs error message:

"VHDL compile skipped for cellview LIB1.cell1:entity
because view name is 'entity"

View list: entity, schematic, symbol.

What this error means?

Best Regards.

Pavel.

Thank you for answer Stefan.

I tried also with architecture

View list: entity, arch1, schematic, symbol

where arch1 - architecture view.

Nothing changed.