OK, I'm ready to actually use this tool.  My understanding is that AMS is a superset of verilog-A and verilog-D.  So to get started, I type in the following program:

module top();
initial
 begin
  $display("Hello World!");
  $finish;
 end
endmodule

This works fine in verilog-D.  From Ken's book, I know to type

 ncvlog -ams hello_world.v  

And I actually get an empty ncvlog.log file.  But no friendly greeting of " Hello World!"  from my computer.  Can anyone help me get past this first baby step into the glorious world of mixed-mode simulation?

 thanks in advance for your attention,
 Joel

 

I'm doing OK so far.  I've typed in a few examples from Ken's book, and gotten them to run.  But can anyone tell me how to generate a dump file?  The traditional $dumpon doesn't seem to produce anything.  Thanks!

I found a method here:

http://www.designers-guide.org/Forum/YaBB.pl?num=1191611485

I'm disappointed I can't view analog and digital waveforms with the same tool, but I guess getting the simulations to interact is the main thing.

Thanks all!  One last question:  Is it possible to dump ascii tabular files of analog voltages/currents/etc., like the spice .print command does?  I tend to do postprocessing using perl, matlab, or whatever, and I find this a convenient format.  Cheers!  /jd

Simvision (which you get if you run ncsim -gui )
does support viewing both analog and digital signals..
none of that "dump" stuff is needed, just setup probe commands in the tcl file you pass to the simulation..
--
Why is it so complicated ?
because most of us need different compilation options for different parts of the design.. some blocks need to be compiled with -ams (for analog )
sometimes we also use VHDL so we compile with ncvhdl..
and digital stuff we compile without the -ams option.
-- then when we have everything compiled.. we'll establish a configuration we need to simulation, and we have to LINK all these objects together (and add connect modules etc etc..) this is the "elaboration"..
then once we have an elaboration snapshot, we can actually start one or more simulations.. (ncsim)
--
most of us actually have something more like MAKE, that takes all the source code, and compiles each bit with the right options, into the appropriate lib, does the elaboration.. and then starts a sim..
Cadence provides NCVERILOG which follows closely the command line options from VERILOGXL -- and more recently they support an "irun" option which I plan to study soon..

HTH
jbd

Instructions for starting cadence and the simulators vary widely from site to site.. I'd suggest asking your CAD manager first..
There is also a lot of documentation on the CADENCE website.. and courses available from them .. um YES registration is required to get at the documentation, and you will need to know your companies License server hostID (the one hosting the cadence keys) .

you might be able to find a consultant in your area who can help you get up to speed.. I would not be expecting such a service to be free.

I've been listening to the StackOverflow podcasts this weekend and am not Satisfied with leaving the answer at this.. as it seems to shut out those who may not have access to real help on this.

There are other tools - some that are free..
there are fewer people working on this than on linux or gaming machines, so the talent pool to help you up the curve is small. YOU will have to invest a lot of your own research - study - and trial and error to get up the curve unless you are have graduated and are work in this field.  you'll probably have to put that BSEE to work and may need to know some software skills too.. and MSEE will help too.

For free tools look at GEDA (Gnu Electronic Design Automation) --
for straight digital verilog there is Icarus verilog..
for spice like simulations I've heard good things about Gnucap. But 2 years after hearing about this, I STILL haven't finished the setup and testing of this app. (Ideally I should be able to add it to my Fedora Install and run.. the version picked up by Ubuntu is pretty old I think.
so to get this working youll need to follow instructions on the website, and MAKE your own install, and them Fix any issues with that before you have something working..

Pretty much we are in a similar position today that the OS World was in in 1995.. back when the choices were Unix or Windows.  There actually were versions of Linux around but it was pretty much a toy for hobbyists at that point. -- and People needing to get real work bought software for either Unix or Windows..
Right now the gulf in functionality between the very expensive commercial software and the free tools means that companies that want to get Chips out the door, for the most part cannot afford to use the free tools.. Its much more effecitve right now to buy full featured tools for the engineers to use, and use the same tools as are used in most other companies so its not too hard to hire folks with enough knowledge to use them.
So MOST of us on this forum are using the expensive tools, courtesy of our employers - and setup by our CAD folks.. so that WE can do design (or design Verification in my case)
hopefull the Geda and (open eda?) and gnucap websites will help you.

MY favorite editor is nedit - since there are pattern files for it..
but if you are used to VIM, I think those pattern files (the name is different) are available on this forum somewhere..
and emacs has a verilog-A and Verilog-AMS modes available somewhere too..

AfTER starting cadence, BEFORE opening a new cellview,
in the CIW window type (they taught you about this part right?)

editor = "nedit"

- you can substitute the command for your favorite editor, but vi is the cadence default.
Then go to the library manager, select the library you want to create a model in, and then use the File -> New -> Cellview
pull down menu.. (just like creating a new schematic symbol or layout view)
but pick Verilog-A editor (or Verilog-AMS editor if doing mixed signal)
or Verilog editor if doing digital)
for the Tool, and use an appropriate view name, (cadence defaults to veriloga or verilogams respectively - but I find I sometimes need more views depending on what I'm connected to it, so we have standardized a few other view names.  ie vlog_empty, vloga_basebandeq, etc
if you pick the digital tool, there is no default, but "functional" or "behavioral" are traditional verilog view names.

---
after deciding which cell,  view name and tool
click ok
--
and your selected editor will open , populated with as much information as cadence has about that view (ie if the symbol or schematic view exist you'll get a module declaration with pins.. if not, you'll just get an empty module declaration.)

Edit the model
SAVE and exit the editor.
at this point a syntax checker will run..
fix the syntax errors
save and exit,
fix the syntax errors,
save and exit...
and if you have fixed them all, (and there is no symbol, or if the new pin info is different from the old symbol)
then it will ask you if you want to CREATE (or replace or modify) the symbol view.

then you build a schematic with your model and any stimulus you want to test it with (ie borrowed from ahdlLib  or bmslib )
or analoglib
when your testbench is done,
fire up ADE pick an appropriate simulator (spectre for verilogA, ams for anything else) netlist and run.
--
I'm assuming your instructor set up any connect modules you'll need.

don't forget how to fire up the cadence docs (cdnshelp or cdsdoc depending on the version of the TOOL you want to find help on)

Your school has someone with access to cadence training manuals, and cadence AE's..  find out who that person is. (chances are , if you get any good at this, you'll be able to take on that TA position next school year -- unless the line for this position is long. )

Good luck