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Hoody

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Measure delay with sweep in SPICE
Aug 06^th, 2008, 4:37pm

Dear all,

I plan to calibrate the delay of a logic gate with different cap load. I want to sweep the cap load and then measure the delay of each load. How can I use Verilog-A to accomplish the task?

I know how to use Verilog-A to measure a single delay. But I don't know how to integrate the Verilog-A code to a sweep simulation.

Thanks.

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Geoffrey_Coram Senior Fellow Offline Posts: 1999 Massachusetts, USA	Re: Measure delay with sweep in SPICE Reply #1 - Aug 8^th, 2008, 8:32am Verilog-A is a hardware description language (HDL) not a measurement description language (MDL), so I'm not sure you really want to do this with Verilog-A.
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Hoody

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Re: Measure delay with sweep in SPICE
Reply #2 - Aug 8^th, 2008, 9:50am

Geoffrey_Coram wrote on Aug 8^th, 2008, 8:32am:

Verilog-A is a hardware description language (HDL) not a measurement description language (MDL), so I'm not sure you really want to do this with Verilog-A.

Verilog-a has functions allows you to do measurement. For example, if you want to measure the delay of an inverter, you can use the cross function to detect the rise of the input signal, assign the time to a variable, say t0. Then you use cross to detect the falling of the output signal, assign the time to a variable t1. The delay is t1-t0.

Kundert described this in his Verilog AMS book chapter 3, section 9 Time interval measurement.

My problem is how to use this method with step function in SPICE. I can use the above function to measure delay with one capacitor load. If I want to step the capacitor load, I wanted to use some code to compute each delay for different load, then at the end, I can do some math for the delays.

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jbdavid

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Re: Measure delay with sweep in SPICE
Reply #3 - Aug 9^th, 2008, 7:26am

I've not used spice in a long time, so I can no longer comment on using STEP..
but If I were approaching this task.. I'd make a load model where I integrreated I/C to get V then set C to a new value once V returned to 0
and the prior measurement was complete.
for single components like this I tend to prefer using the derivative form
I = Cdvdt .. but it in this case it can have the side effect of creating/destroying "charge" (which is not realistic) if you change the value of C with a non-zero voltage.
Not much of a problem on the testbench but it could lead to serious errors if you make this a habit, then model a real circuit this way.

(see prior discussions on modeling voltage dependent capacitors.. )
but to answer your question, If I had a spec for a circuit on delay with various load caps, this would be my approach to measuring it during simulation. (the alternative being a powerful post processing environment)
jbd

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jbdavid
Mixed Signal Design Verification

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Geoffrey_Coram

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Re: Measure delay with sweep in SPICE
Reply #4 - Aug 11^th, 2008, 5:01am

Could you STEP an integer parameter and pass this value to the Verilog-A model, which would use the integer to index an array of capacitor values and to store the result of the delay measurement?

It may depend, too, on how your Spice simulator resets the models for a STEP; it may be that STEP is just a shorthand for independent transient analyses with ALTERs, and your model will be reset, losing the measured delay from the previous run. As I said, Verilog-A is not really intended as an MDL.

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