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sprun

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A doubt on verilog-A syntax
Aug 12^th, 2008, 11:19pm

Hi everyone, I'm a fresh here and also in verilog-A. I learned some verilog-A basics to modelling a charge pump circuit required by our project recently. However, I found a problem when running my verilog-A code in spectre.

The case is, whenever I put a <+ sentence after a @ sentence in the code, that is,

@(expression)
begin
expression <+ expression;
end

a hint for covergence problem will appear once I run the code.

I don't know why this happens. But I do see some demo verilog-A code use the two sentences in this way. I also tried some of these demo code, but they have the same problem!

Do anyone have the same experience? Can anyone help me to solve this problem? Thanks!

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ywguo Community Fellow Offline Posts: 943 Shanghai, PRC	Re: A doubt on verilog-A syntax Reply #1 - Aug 13^th, 2008, 2:00am Hi sprun, It looks that it is a hint for warning that probably there is a convergence problem. That is not a syntax error. Would you please show your code here or an example which have the problem? Yawei
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sprun

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Re: A doubt on verilog-A syntax
Reply #2 - Aug 13^th, 2008, 2:47am

Hi Yawei,

Thanks for your attention!
The following is my code:

`include "constants.vams"
`include "disciplines.vams"

module pump(clk,out);

input clk;
output out;

electrical clk, in, out;

real odd;

parameter real C = 1.0e-12;
parameter real VDD = 3.3;
parameter real Vth = 0.6;
parameter real f = 1e7; //freq=10MHz
parameter real N = 4; //pump stage

analog begin

odd = N%2;

@(initial_step)
begin
V(out) <+ 0;
end

@(above(V(clk) - 1.6))
� begin

�if(V(out) > (VDD - 1.2))
begin
� �V(in) <+ VDD+N*VDD-(N+1.0)*Vth;
� �V(out,in) <+ (N/(f*C))*I(in,out);
end
�else
begin
� �V(in) <+ VDD+N*VDD-(N+1.0)*Vth;
� �V(out,in) <+ 35.0e3*I(in,out);
end
�end
�
I(in,out) <+ ((4.0*N*N-N-3.0)*C/(12.0*(N+1.0)))*ddt(V(out))*odd + ((4.0*N*N+3.0*N+2.0))*C/(12.0*(N+1.0))*ddt(V(out))*(1-odd);

� end

end

endmodule

__________________________________________________________

Kindly please help to debug it. Thanks a lot!

ywguo wrote on Aug 13^th, 2008, 2:00am:

Hi sprun,

It looks that it is a hint for warning that probably there is a convergence problem. That is not a syntax error. Would you please show your code here or an example which have the problem?

Yawei

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Geoffrey_Coram

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Re: A doubt on verilog-A syntax
Reply #3 - Aug 13^th, 2008, 6:21am

sprun wrote on Aug 12^th, 2008, 11:19pm:

@(expression)
begin
expression <+ expression;
end

I believe that syntax is illegal; namely, you shouldn't have a contribution (<+) inside an event. You should do something instead like:

real outval;

analog begin
@(initial_step) outval = 0;
@(expression) begin
outval = 5;
end
I(out) <+ outval;

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sprun

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Re: A doubt on verilog-A syntax
Reply #4 - Aug 13^th, 2008, 6:43pm

Hi Geoffrey_Coram.!

You mean the syntax is indeed wrong and I have to define another variable to pass the value to avoid the wrong syntax, right?

But why a contribution (<+) cannot be included in a event (@)? Could you explain the reason?

I mentioned above that I have seen some demo code in some books and they just used the 'wrong' syntax. Seems that they didn't treat it wrong.

Geoffrey_Coram wrote on Aug 13^th, 2008, 6:21am:

sprun wrote on Aug 12^th, 2008, 11:19pm:

@(expression)
begin
expression <+ expression;
end

I believe that syntax is illegal; namely, you shouldn't have a contribution (<+) inside an event. �You should do something instead like:

real outval;

analog begin
�@(initial_step) outval = 0;
�@(expression) begin
� �outval = 5;
�end
�I(out) <+ outval;

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Geoffrey_Coram

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Posts: 1999
Massachusetts, USA

Re: A doubt on verilog-A syntax
Reply #5 - Aug 14^th, 2008, 7:58am

sprun wrote on Aug 13^th, 2008, 6:43pm:

Hi Geoffrey_Coram.!

You mean the syntax is indeed wrong and I have to define another variable to pass the value to avoid the wrong syntax, right?

But why a contribution (<+) cannot be included in a event (@)? Could you explain the reason?

I mentioned above that I have seen some demo code in some books and they just used the 'wrong' syntax. Seems that they didn't treat it wrong.

What books? Were they on Verilog-A, or are you translating a digital assignment syntax to analog? The Verilog-AMS LRM explicitly forbids this (see Section 5.10, specifically the bullets on page 109 (124 of 402 in the PDF) of the latest LRM 2.3).

The issue is, if the contribution is only in the event, what is supposed to happen for all iterations of all timepoints when the event is not triggered? Answer: no contribution at all. It would be a huge convergence disaster if you were contributing 5A at one timepoint and nothing (open circuit) at the next.

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If at first you do succeed, STOP, raise your standards, and stop wasting your time.

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sprun

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Re: A doubt on verilog-A syntax
Reply #6 - Aug 14^th, 2008, 6:38pm

Thank you! I also found the warning in The Designer's Guide to Verilog-AMS yesterday. Seems that I have to avoid putting a contribution in an event. Thanks anyway!

Geoffrey_Coram wrote on Aug 14^th, 2008, 7:58am:

sprun wrote on Aug 13^th, 2008, 6:43pm:

Hi Geoffrey_Coram.!

You mean the syntax is indeed wrong and I have to define another variable to pass the value to avoid the wrong syntax, right?

But why a contribution (<+) cannot be included in a event (@)? Could you explain the reason?

I mentioned above that I have seen some demo code in some books and they just used the 'wrong' syntax. Seems that they didn't treat it wrong. �

What books? �Were they on Verilog-A, or are you translating a digital assignment syntax to analog? �The Verilog-AMS LRM explicitly forbids this (see Section 5.10, specifically the bullets on page 109 (124 of 402 in the PDF) of the latest LRM 2.3).

The issue is, if the contribution is only in the event, what is supposed to happen for all iterations of all timepoints when the event is not triggered? �Answer: no contribution at all. �It would be a huge convergence disaster if you were contributing 5A at one timepoint and nothing (open circuit) at the next.

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