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if statement (Read 1952 times)
sprun
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if statement
Aug 18th, 2008, 2:33am
 
Hi everyone, I have another problem when writing my verilog-A code. The case is whenever I put a if statement embedded in another if statement, the simulation cannot even start.

Is this another forbidden in verilog-A syntax? But I didn't found it. Hope somebody could help. Thanks a lot!
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Geoffrey_Coram
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Re: if statement
Reply #1 - Aug 20th, 2008, 6:36am
 
It's not forbidden to have nested if statements.  What's going inside the if statements, though, could cause trouble.  I'd try a simple assignment, such as:
Code:
if (x > 0) begin
  if (x > 10)
    y = 6;
  else
    y = 8;
end else begin
  y = 0;
end
I(out) <+ y; 



and see if your simulator has trouble with that.

Another thing to watch out for is making sure you've got your "else" associated with the correct "if" -- indentation is not significant, so:
Code:
if (x > 0)
  if (x > 10)
    y = 6;
else
  y = 8; 


the "else" on line 4 corresponds with the "if" on line 2, not the line 1 that it's indented to match.
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