Hi,

What are the W & L here? Are these the W & L of the gate? Then, your formulae are all wrong.

You cannot know the diffusion dimensions for source & drain just by looking at the schematic. This
depends on the minimum width allowed for these by the design rules.

If I consider source or drain, then 1 dimension (let's call it the length, Ldiff) equals the width of your gate.

So, Ldiff = W

As for Wdiff, this depends on the design rules as I mentioned. So you need to instantiate the layout of a unit transistor of interest, and see how wide the diffusion there is. In a 0.5 um process, this may for instance be 0.8 um.

Then, you can compute ad(as) and pd(ps) by substituting Wdiff and Ldiff in the formulae you present here.

On more advanced features:
Naturally, you need to guarantee that you are using the same diffusion width Wdiff for all transistors. The minimum is fixed by design rules, but you may make a poor layout, or have other reasons to dimension differently, and get a higher Wdiff, or not a constant Wdiff for all transistors. Moreover, if you make multi-finger transistors, then adjacent transistors share the same diffusion implant. Thus, the effective area ad(as) and pd(ps) are reduced by a factor of 2.

Regards,
Vivek

xwj623 wrote on Aug 20^th, 2008, 12:07am:


1. Correct !!!
2. I don't know either, but I don't think the gate edge is included. So, I would use ps=2*(w+Ldif). In any case, models which include the effect of the gate edge already will usually also include the ad/as/pd/ps parameters automatically.
3. I don't think so, but again, I don't know. Usually, LD is small and you should be able to ignore it.

But the basic form of equations you have ought to be enough to model everything quite accurately.

Regards,
Vivek

xwj623 wrote on Aug 20^th, 2008, 12:07am:


BSIM4 has a parameter, PERMOD, which determines how the gate edge is computed; sometimes the gate edge junction capacitance differs significantly from the isolation edge junction capacitance.