vivkr
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Hi,
What are the W & L here? Are these the W & L of the gate? Then, your formulae are all wrong.
You cannot know the diffusion dimensions for source & drain just by looking at the schematic. This depends on the minimum width allowed for these by the design rules.
If I consider source or drain, then 1 dimension (let's call it the length, Ldiff) equals the width of your gate.
So, Ldiff = W
As for Wdiff, this depends on the design rules as I mentioned. So you need to instantiate the layout of a unit transistor of interest, and see how wide the diffusion there is. In a 0.5 um process, this may for instance be 0.8 um. Then, you can compute ad(as) and pd(ps) by substituting Wdiff and Ldiff in the formulae you present here.
On more advanced features: Naturally, you need to guarantee that you are using the same diffusion width Wdiff for all transistors. The minimum is fixed by design rules, but you may make a poor layout, or have other reasons to dimension differently, and get a higher Wdiff, or not a constant Wdiff for all transistors. Moreover, if you make multi-finger transistors, then adjacent transistors share the same diffusion implant. Thus, the effective area ad(as) and pd(ps) are reduced by a factor of 2.
Regards, Vivek
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