Forum
Forum
Verilog-AMS
Analysis
Modeling
Design
Theory
Welcome, Guest. Please
Login
or
Register.
Please follow the Forum
guidelines
.
Aug 16
th
, 2024, 6:39pm
Home
Help
Search
Login
Register
PM to admin
The Designer's Guide Community Forum
›
Design Languages
›
Verilog-AMS
› verilog-A model for counter
‹
Previous topic
|
Next topic
›
Pages: 1
verilog-A model for counter (Read 8141 times)
smarty
Community Member
Offline
Posts: 46
verilog-A model for counter
Aug 28
th
, 2008, 7:36am
Hi all,
I am designing a temperature sensor and I would need to design a counter. But I wanted to test my design using behavioral model (verilog-A) model of counter.
I am not an expert in modelling. Can anybody help me out on this.
I need a counter which takes in serial input and converts it into a 8-bit parallel data.
Thanks and Regards,
SBR
Back to top
IP Logged
jbdavid
Community Fellow
Offline
Posts: 378
Silicon Valley
Re: verilog-A model for counter
Reply #1 -
Aug 28
th
, 2008, 11:36am
if you are using Cadence tools there are two libraries of interest shipped with the tools, ahdlLib, and bmslib.. there are examples of what you are looking for in there.
Also there are examples here on this site that may help you out.
jbd
Back to top
jbdavid
Mixed Signal Design Verification
IP Logged
smarty
Community Member
Offline
Posts: 46
Re: verilog-A model for counter
Reply #2 -
Aug 28
th
, 2008, 8:19pm
Hi jbd,
Thanks.. I am working with cadence. i will look for the two libraries u mentioned and also search this site, if I get a little bit more info.
Best Regards,
SBR
Back to top
IP Logged
Pages: 1
‹
Previous topic
|
Next topic
›
Forum Jump »
» 10 most recent Posts
» 10 most recent Topics
Design
- RF Design
- Analog Design
- Mixed-Signal Design
- High-Speed I/O Design
- High-Power Design
- Mixed-Technology Design
Analog Verification
- Analog Functional Verification
- Analog Performance Verification
Measurements
- RF Measurements
- Phase Noise and Jitter Measurements
- Other Measurements
Modeling
- Semiconductor Devices
- Passive Devices
- Behavioral Models
- Transmission Lines and Other Distributed Devices
Design Languages
»» Verilog-AMS
- VHDL-AMS
Simulators
- Circuit Simulators
- RF Simulators
- AMS Simulators
- Timing Simulators
- System Simulators
- Logic Simulators
Other CAD Tools
- Entry Tools
- Physical Verification, Extraction and Analysis
- Unmet Needs in Analog CAD
General
- Tech Talk
- News
- Comments and Suggestions
- Opportunities
« Home
‹ Board
The Designer's Guide Community Forum
» Powered by
YaBB 2.2.2
!
YaBB
© 2000-2008. All Rights Reserved.
Copyright 2002-2024
Designer’s Guide Consulting, Inc.
Designer’s Guide
® is a registered trademark of
Designer’s Guide Consulting, Inc.
All rights reserved.
Send comments or questions to
editor@designers-guide.org
. Consider
submitting
a paper or model.